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NTP13N10
Preferred Device
Power MOSFET
13 A, 100 V, N-Channel Enhancement-Mode TO-220
Features
* Source-to-Drain Diode Recovery Time Comparable to a Discrete * * *
Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Pb-Free Package is Available
VDSS 100 V
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RDS(ON) TYP 165 m @ 10 V N-Channel D ID MAX 13 A
Typical Applications
* PWM Motor Controls * Power Supplies * Converters
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Source Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous - Non-Repetitive (tpv10 ms) Drain Current - Continuous @ TA 25C - Continuous @ TA 100C - Pulsed (Note 1) Total Power Dissipation @ TA = 25C Derate above 25C Operating and Storage Temperature Range Single Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 13 A, L = 1.0 mH, RG = 25 ) Thermal Resistance - Junction-to-Case Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID Value 100 100 "20 "30 Adc 13 8.0 39 64.7 0.43 -55 to +175 W W/C C mJ 85 C/W C 13N10 A Y WW 1 2 3 4 Unit Vdc Vdc Vdc G
S
MARKING DIAGRAM & PIN ASSIGNMENT
4 Drain
IDM PD TJ, Tstg EAS
TO-220AB CASE 221A STYLE 5 1 Gate
13N10 AYWW 3 Source 2 Drain
RJC TL
2.32 260
= Device Code = Assembly Location = Year = Work Week
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
ORDERING INFORMATION
Device NTP13N10 NTP13N10G Package TO-220AB TO-220AB (Pb-Free) Shipping 50 Units/Rail 50 Units/Rail
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Preferred devices are recommended choices for future use and best overall value.
(c) Semiconductor Components Industries, LLC, 2006
August, 2006 - Rev. 6
1
Publication Order Number: NTP13N10/D
NTP13N10
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Collector Current (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 25C) (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS Gate Threshold Voltage VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) Static Drain-to-Source On-State Resistance (VGS = 10 Vdc, ID = 6.5 Adc) (VGS = 10 Vdc, ID = 6.5 Adc, TJ = 125C) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 13 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 6.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 2 & 3) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 80 Vdc, ID = 13 Adc, VGS = 10 Vdc) BODY-DRAIN DIODE RATINGS (Note 2) Forward On-Voltage Reverse Recovery Time (IS = 13 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 2. Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperature. (IS = 13 Adc, VGS = 0 Vdc) (IS = 13 Adc, VGS = 0 Vdc, TJ = 125C) VSD trr ta tb QRR - - - - - - 0.98 0.88 85 60 28 0.3 1.3 - - - - - mC Vdc ns (VDD = 80 Vdc, ID = 13 Adc, VGS = 10 Vdc, RG = 9.1 ) td(on) tr td(off) tf Qtot Qgs Qgd - - - - - - - 11 40 20 36 14 3.0 7.0 20 80 40 70 20 - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 390 115 35 550 160 70 pF VGS(th) Vdc 2.0 - - - - - 3.2 -7.6 0.130 0.250 1.82 6.0 4.0 - 0.165 0.400 2.34 - mhos mV/C V(BR)DSS Vdc 100 - - - - - 147 - - - - - 5.0 50 100 mV/C mAdc Symbol Min Typ Max Unit
IDSS
IGSS
nAdc
RDS(on)
VDS(on) gFS
Vdc
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NTP13N10
26 24 22 20 18 16 14 12 10 8 6 4 2 0 VGS = 10 V 9V 8V 7.5 V 6V 5.5 V 5V 4.5 V 0 8 9 1 2 3 4 5 6 7 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 7V 6.5 V TJ = 25C ID, DRAIN CURRENT (AMPS) 26 24 22 20 18 16 14 12 10 8 6 4 2 0 VDS 10 V
ID, DRAIN CURRENT (AMPS)
TJ = 25C TJ = 100C 0 TJ = -55C 10
1 2 3 4 5 6 7 8 9 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.5 0.4 0.3 0.2 0.1 0
VGS = 10 V
0.2 TJ = 25C
0.175
TJ = 100C
0.15
VGS = 10 V VGS = 15 V
TJ = 25C TJ = -55C
0.125
0
2
4
6 8 10 12 14 16 18 20 22 24 ID, DRAIN CURRENT (AMPS)
26
0.1
0
2
4
6 8 10 12 14 16 18 20 22 24 26 ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 4. On-Resistance versus Drain Current and Gate Voltage
3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) 175 ID = 6.5 A VGS = 10 V
10,000
VGS = 0 V
IDSS, LEAKAGE (nA)
1000
TJ = 150C
100 TJ = 100C 10 20 30 60 70 80 90 100 40 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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NTP13N10
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1000 800 600 Crss 400 200 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
VDS = 0 V Ciss
VGS = 0 V
TJ = 25C
C, CAPACITANCE (pF)
Coss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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NTP13N10
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 20 18 16 14 12 10 8 6 4 2 0 0 2 4 6 8 10 QG, TOTAL GATE CHARGE (nC) ID = 13 A TJ = 25C 12 Q1 Q2 VGS VDS QT 100 90 80 70 60 50 40 30 20 10 0 14 1000 VDD = 80 V ID = 13 A VGS = 10 V 100 t, TIME (ns) tr tf
10
td(off)
td(on)
1
1
10 RG, GATE RESISTANCE ()
100
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
12 IS, SOURCE CURRENT (AMPS) 10 8 6 4 2 0 0.4 VGS = 0 V TJ = 25C
0.5
0.6
0.7
0.8
0.9
1
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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NTP13N10
SAFE OPERATING AREA
100 ID, DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C 10 10 s 100 s 1 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 dc
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)
100 ID = 13 A 80
60
40 20 0 25
10 1 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
1 D = 0.5
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
0.2 0.1 0.05 0.01 SINGLE PULSE 0.001 0.01 t, TIME (s) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 1 10
t2 DUTY CYCLE, D = t1/t2 0.1
t1
0.1 0.0001
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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NTP13N10
PACKAGE DIMENSIONS
TO-220 THREE-LEAD TO-220AB CASE 221A-09 ISSUE AA
-T- B
4
SEATING PLANE
F
T
C S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04
Q
123
A U K
H Z L V G D N
R J
STYLE 5: PIN 1. 2. 3. 4.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NTP13N10/D

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